1. Field of the Invention
The present invention relates to a parallel test circuit of a semiconductor memory device, and more particularly to a parallel test circuit of a semiconductor memory device which has a divided output driver configuration capable of achieving an accurate parallel test.
2. Description of the Prior Art
Semiconductor memory devices, which may be dynamic random access memories (DRAMs), have been rapidly improved to have an increased density. Recently, semiconductor devices themselves have been developed to have an ultra-high density up to a degree that several ten million cells are included in one semiconductor device. Meanwhile, it is very important to test whether cells are normal or abnormal. This test should not only be accurately conducted, but also be rapidly achieved. In order to meet such requirements, a parallel test method has been proposed in which a simultaneous multi-bit access can be achieved. This parallel test method has been commonly used in the technical field to which the present invention pertains. In order to reduce the test time, most DRAMs are equipped with parallel test circuits.
Referring to FIG. 1, a conventional parallel test circuit is illustrated. As shown in FIG. 1, the parallel test circuit includes a data input pad DIN, to which data to be written is inputted, and a pair of cell arrays, that is, a first cell array 2A and a second cell array 2B, each consisting of a plurality of memory cells each adapted to store the data inputted to the data input pad DIN. Also, there is an output driver 8 which is switched, in accordance with respective data A and B stored in the first and second cell arrays 2A and 2B, between a normal mode, in which it outputs the stored data A and B, and a test mode in which it outputs a signal having a high or low level selected on the basis of the levels of the stored data A and B. The parallel test circuit also includes a first switch SW1 for selectively coupling the input data from the data input pad DIN to a normal path or a test path, a second switch SW2 for selectively coupling the data inputted via the normal path to the first cell array 2A or second cell array 2B in the normal mode, and a third switch SW3 for selectively outputting the first data A stored in the first cell array 2A or the second data B stored in the second cell array 2B via the normal path in the normal mode. The parallel test circuit further includes an inverter INV1 for inverting the data selectively outputted in accordance with a switching operation of the third switch SW3, an output driver control unit 4 for outputting a first output driver driving signal DR1 and a second output driver driving signal DR2 adapted to control an output driver 8 in the test mode, based on the data A and B from the first and second cell array 2A and 2B, respectively, and a fourth switch SW4 for selectively coupling the data selectively outputted in accordance with the switching operation of the third switch SW3 or the first output driver driving signal DR1 from the output driver control unit 4 to the output driver 8. The parallel test circuit also includes a fifth switch SW5 for selectively coupling the output from the first inverter INV1 or the second output driver driving signal DR2 from the output driver control unit 4 to the output driver 8, and a data output pad DOUT for externally outputting the output from the output driver 8 when the data is to be read.
The output driver control unit 4 includes an exclusive NOR gate XNOR for exclusively NORing the output data A and B from the first and second cell arrays 2A and 2B, and a second inverter INV2 for inverting the output from the exclusive NOR gate XNOR, thereby outputting the inverted signal as the second output driver driving signal DR2.
The output driver 8 includes a pair of NMOS transistors NM1 and NM2 coupled in series between a supply voltage Vcc and a ground voltage Vss. The first NMOS transistor NM1 receives, at its gate, the signal selectively outputted via the second switch SW2 whereas the second NMOS transistor NM2 receives, at its gate, the signal selectively outputted via the third switch SW3. The node between the first and second NMOS transistors NM1 and NM2 is coupled to the data output pad DOUT, so that an output signal thereon is outputted to the data output pad DOUT.
The conventional parallel test circuit having the above mentioned configuration operates in such a method that it outputs a signal having a logic xe2x80x98highxe2x80x99 level when cells, which are parallel-accessed, are stored with the same data while outputting a logic xe2x80x98lowxe2x80x99 level when those cells are stored with different data, respectively. When the parallel test circuit outputs a signal having a logic xe2x80x98highxe2x80x99 level, the semiconductor device tested by the parallel test circuit is regarded as to have passed. On the other hand, when the parallel test circuit outputs a signal having a logic xe2x80x98lowxe2x80x99 level, the semiconductor device is regarded as to have failed.
FIG. 2 is a truth table for the parallel test mode of the conventional parallel test circuit shown in FIG. 1. As shown in FIG. 2, where respective output data A and B of the first and second cell array 2A and 2B are identical to each other, a signal having a value of xe2x80x981xe2x80x99, namely, a logic xe2x80x98highxe2x80x99 level, is output from the data output pad DOUT of the parallel test circuit in a read mode. Where the output data A and B of the first and second cell array 2A and 2B are different from each other, a signal having a value of xe2x80x980xe2x80x99, namely, a logic xe2x80x98lowxe2x80x99 level, is output from the data output pad DOUT.
However, where all of parallel-accessed cells have the same data, various problems may occur in the above mentioned conventional parallel test circuit because an output having a xe2x80x98highxe2x80x99 level is always generated in this state, irrespective of the value of the data. For instance, although the first and second cell arrays 2A and 2B of FIG. 1, which are parallel-accessed to be written with data of xe2x80x981xe2x80x99, are erroneously stored with data of xe2x80x980xe2x80x99, an output of a xe2x80x98highxe2x80x99 level is generated in accordance with the conventional parallel test method. Due to the xe2x80x98highxe2x80x99-level output, the associated semiconductor device is erroneously detected to be passed. In other words, the test operation of the parallel test circuit itself is erroneously conducted. Thus, the conventional parallel test method using the configuration of FIG. 1 cannot detect the above mentioned error. In accordance with the conventional parallel test method, an output of a xe2x80x98highxe2x80x99 level is always generated for semiconductor devices having a good quality. For this reason, the conventional parallel test method cannot be used for a test of checking device characteristics or for a speed sort test, which tests need either output of a xe2x80x98highxe2x80x99 or xe2x80x98lowxe2x80x99 level.
Therefore, the present invention has been made in view of the above mentioned problems, and an object of the invention is to provide a parallel test circuit capable of conducting an accurate parallel test even when erroneous data is stored due to an erroneous operation.
Another object of the invention is to provide a parallel test circuit capable of accurately detecting errors involved in a semiconductor memory circuit, in which the parallel test circuit is incorporated, so that it can not only conduct a reliable parallel test for pass/fail devices, but also be used to check device characteristics or for a speed sort test.
In accordance with the present invention, these objects are accomplished by providing a parallel test circuit for a semiconductor memory device comprising a data input pad, to which data to be written is inputted, a plurality of cell arrays each consisting of a plurality of memory cells each adapted to store the data inputted to the data input pad, and a data output pad for outputting the stored data when the stored data is to be read, further comprising: a main output driver for, when the cell arrays are stored with data having the same level, respectively, outputting a signal having the same level as the stored data; a sub output driver for, when the cell arrays are stored with data having different levels, respectively, outputting a signal having an intermediate level; a main output driver control unit activated by an output enable signal and adapted to control the main output driver in accordance with the levels of the data stored in the cell arrays; and a sub output driver control unit activated by the output enable signal and adapted to control the sub output driver in accordance with the levels of the data stored in the cell arrays.
In accordance with an embodiment of the present invention, the intermediate level corresponds to a low impedance level.
In accordance with an embodiment of the present invention, the intermediate level corresponds to half the level of a supply voltage.
In accordance with an embodiment of the present invention, the main output driver has a current capacity higher than that of the sub output driver.
In accordance with an embodiment of the present invention, the parallel test circuit further comprises delay means for floating the sub output driver after the sub output driver outputs data for a desired period of time, thereby cutting off the outputting of data from the sub output driver.
In accordance with an embodiment of the present invention, the sub output driver control unit comprises first comparing means for comparing data outputted from the sub output driver with a first reference voltage, thereby outputting a first sub driving signal, and second comparing means for comparing the data outputted from the sub output driver with a second reference voltage, thereby outputting a second sub driving signal, the first and second comparing means being activated by a combination of the output enable signal with a combination of the data respectively stored in the cell arrays.
In accordance with an embodiment of the present invention, each of the first and second comparing means is a current mirror type sense amplifier.
In accordance with an embodiment of the present invention, the first reference voltage has a level corresponding to 0.54 times the level of a supply voltage, and the second reference voltage has a level corresponding to 0.32 times the supply voltage level.